We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.

We present two types of ICF (INHIBIT Controlled by Fluxon) gates as the basic circuits of the phase-mode logic family, and fabricate an adder circuit. The experimental result demonstrates that the carry operation followed up to 99 GHz input pulses. The performance of Josephson devices is improved by the use of junctions with high current density (Jc). We may use the high-Jc junctions without external resistive shunt in the phase-mode logic circuits because of reduction of the junction hysteresis. One of the ways to overcome the large area occupancy for geometric inductance is to utilize the effective inductance of a Josephson junction itself. We investigate a circuit construction with high-Jc inductor junctions, intrinsically overdumped junctions and junction-type resistors for the compactness of circuit integration, and discuss various aspects of the circuit construction.

Logic operations in principle have been demonstrated based on the planar high-Tc Superconducting QUantum Interference Device (SQUID). Two kinds of logic gates were produced by using the focused ion beam (FIB) superconducting weak links fabricated in NdBa2Cu3O7-δ (NBCO) thin films. Logic gates investigated in this paper are (1) an rf-SQUID based logic gate which utilizes threshold characteristics, and (2) a dc-SQUID based logic gate which is an elementary gate of RSFQ circuits. Elementary logic operation such as (1) AND/OR logic and (2) SET-RESET flip-flop operation were successfully obtained in the logic gates. In addition to the present experimental results, some problems and future prospects are also discussed.

A binary counter circuit in the extended phase-mode logic (EPL) family is presented. The EPL family utilizes a single flux quantum as an information bit carrier. Numerical simulations show that a binary counter circuit with a Josephson critical current density of 1 kA/cm2 can operate up to a 30 GHz input signal. The circuit has been fabricated using Nb/AlOx/Nb Josephson junction technology. New interface circuits are employed in the fabricated chip. A low speed test result shows the correct operation of the binary counter.